This research introduces AssertionBench, the first comprehensive benchmark for evaluating LLMs on hardware assertion generation tasks—critical for detecting design bugs in hardware verification.

• Addresses the gap in LLM evaluation for hardware engineering applications
• Evaluates both closed and open-source models on assertion generation capabilities
• Provides insights on model performance across different hardware designs and assertion types
• Reveals limitations in current models when handling complex hardware verification scenarios

For engineering teams, this research provides crucial guidance on which LLMs can effectively assist in automating the labor-intensive process of writing assertions, potentially accelerating verification workflows and improving hardware reliability.

AssertionBench: A Benchmark to Evaluate Large-Language Models for Assertion Generation