This research introduces a novel approach to hardware design by creating a closed-loop system where LLMs generate Verilog code and learn from Electronic Design Automation (EDA) tool feedback.

• Demonstrates how LLMs can automatically debug and improve hardware descriptions after receiving error feedback
• Achieves up to 84% correctness after EDA-guided iterations, compared to 54% in single-shot generation
• Establishes a practical framework for human-machine collaboration in hardware design, reducing engineering effort
• Creates a new dataset of Verilog design challenges with EDA error feedback for future research

This innovation could significantly accelerate hardware development cycles in the semiconductor industry by reducing manual debugging time and enabling more efficient design processes.

Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback