This research introduces a groundbreaking approach to circuit representation learning that preserves logical equivalence while improving electronic design automation.

• Develops a Masked Gate Modeling technique that maintains circuit integrity during training
• Leverages Verilog-AIG alignment to enhance circuit representation learning
• Enables more efficient electronic design automation (EDA) processes
• Demonstrates superior performance on logic synthesis tasks

This innovation matters because it helps engineers create more efficient circuit designs through better automated tools, potentially accelerating development of next-generation electronics and hardware.

Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment