VFlow is a novel framework that automatically discovers optimal sequences of LLM invocations to generate high-quality Verilog code while minimizing computational costs.

• Leverages Monte Carlo Tree Search (MCTS) to find effective workflows rather than using pre-defined prompting strategies
• Optimizes for both code quality and computational efficiency simultaneously
• Extends the AFLOW methodology specifically for hardware design challenges
• Demonstrates significant improvements over existing approaches for Verilog generation

This research offers valuable insights for semiconductor companies seeking to automate hardware design processes, potentially reducing development time and costs while maintaining quality standards.

VFlow: Discovering Optimal Agentic Workflows for Verilog Generation