This research introduces open datasets and benchmarks for evaluating large language models in generating hardware design code (RTL).

• Creates RTLLM 2.0: A comprehensive benchmark for assessing LLM capabilities in RTL generation
• Addresses the critical lack of public datasets that has hindered development in this area
• Establishes a standardized evaluation framework for fair comparison of LLM solutions
• Enables agile circuit design through natural language instructions

This work is significant for hardware engineering as it brings AI-powered automation to chip design workflows, potentially accelerating development cycles and reducing engineering costs.

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation