This research presents a specialized hardware accelerator for matrix multiplication in Transformer models, addressing a critical performance bottleneck in LLM architecture.

• Implements a tiled matrix multiplication approach on resource-constrained FPGA hardware
• Specifically targets the Q, K, and V linear projections in Multi-Head Self-Attention
• Achieves significant performance improvements on the Xilinx KV260 SoM platform
• Demonstrates how hardware acceleration can be optimized for specific AI workloads

This engineering innovation matters because it shows how dedicated hardware solutions can address computational bottlenecks in large language models, potentially enabling more efficient AI deployment in resource-limited environments.

Design and Implementation of an FPGA-Based Tiled Matrix Multiplication Accelerator for Transformer Self-Attention on the Xilinx KV260 SoM