This research addresses the critical challenge of using proprietary IP to fine-tune large language models for Verilog coding while preventing data leakage.

Key Findings:

• Fine-tuning LLMs with proprietary IP data significantly improves Verilog coding capabilities
• However, fine-tuned models can leak sensitive IP through inference attacks
• Design companies face a trade-off between model utility and protecting valuable IP assets
• The research provides a framework for evaluating this security-utility balance

For semiconductor companies and hardware design firms, this research offers crucial insights into the risks of using proprietary designs when developing AI coding assistants, highlighting the need for robust IP protection strategies in LLM deployment.

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding