The VerilogEval benchmark has tracked significant improvements in large language models' ability to generate hardware description code over the past year.

• Models show measurable improvement in generating correct Verilog implementations
• Both commercial and open-source models have advanced in hardware code generation
• Hardware-specific benchmarks reveal capabilities not visible in general coding assessments

This research matters because better LLMs for hardware design could accelerate development cycles, reduce engineering costs, and enable more complex digital systems through automated code generation support.

Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation