CraftRTL introduces a novel approach to generate high-quality synthetic data for training LLMs in hardware description languages like Verilog.

• Addresses challenges in handling non-textual representations such as Karnaugh maps and waveforms
• Implements a correct-by-construction methodology to ensure code accuracy
• Employs targeted code repair to fix common errors in generated Verilog
• Significantly improves LLM performance on hardware design tasks

This research bridges critical gaps in applying AI to engineering disciplines, enabling more reliable automated hardware design processes and potentially accelerating development cycles in digital circuit design.

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair