MetRex introduces a groundbreaking benchmark for evaluating how Large Language Models understand and predict hardware design metrics from Verilog code.

• Created dataset of 25,868 Verilog designs with corresponding metrics
• Tests LLMs' ability to reason about critical post-synthesis metrics
• Analyzes performance across different model sizes and architectures
• Explores practical applications for hardware design optimization

This research enables faster hardware development cycles by potentially reducing the need for time-consuming synthesis steps during early design exploration. Engineers can leverage LLMs to quickly estimate performance metrics before committing to full synthesis processes.

MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs