This research examines how Large Language Models can automate hardware design through High-Level Synthesis (HLS), potentially revolutionizing hardware development workflows.

• Establishes the first comprehensive benchmark for evaluating LLMs in HLS-based hardware generation
• Develops novel infrastructure for generating, validating, and evaluating hardware designs
• Shows that LLMs can generate functional hardware with approximately 80% correctness
• Identifies critical challenges in hardware-specific reasoning that differ from software generation

For engineers, this represents a significant step toward AI-assisted hardware development, potentially reducing design time and enabling exploration of more design alternatives with less manual effort.

Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis