HLS-Eval introduces a novel benchmark and framework to evaluate how effectively large language models can perform high-level synthesis (HLS) design tasks.

• First comprehensive evaluation framework specifically for HLS design workflows
• Addresses a critical gap in LLM evaluation for hardware design beyond Verilog
• Enables measurement of LLM capabilities in creating domain-specific accelerators and complex hardware systems
• Provides tooling for semiconductor designers to assess LLM integration potential

This research is significant for engineering teams as HLS increasingly becomes the preferred approach for designing specialized hardware accelerators. The framework allows engineering teams to make data-driven decisions about incorporating AI assistance in hardware design workflows.

HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks