ResBench introduces the first benchmark for evaluating LLM-generated hardware designs that prioritizes both functional correctness and resource efficiency.

• Addresses a critical gap in existing benchmarks that overlook hardware resource usage
• Provides a more diverse and representative evaluation framework for FPGA implementations
• Enables assessment of LLMs' ability to generate resource-optimized HDL code

This research matters because efficient FPGA design is essential for performance-critical applications in engineering, where optimizing hardware resources directly impacts system capabilities, power consumption, and manufacturing costs.

ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness