This research introduces a novel approach to automate hardware verification in complex SoC designs, potentially reducing the 70% of development time currently spent on verification.

• Creates a specialized SystemVerilog assertion dataset to improve LLM training
• Addresses limitations in proprietary models like GPT-4o that generate inaccurate assertions
• Offers a cost-effective alternative to expensive commercial solutions
• Targets growing complexity challenges in modern hardware systems

For engineering teams, this research represents a significant advancement toward automating a traditionally manual, time-intensive process, enabling more efficient SoC design workflows and potentially faster time-to-market.

Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset