This research introduces an innovative methodology for automatically generating realistic Verilog designs to address the critical shortage of benchmarks for testing Electronic Design Automation tools.

• Creates syntactically valid and semantically meaningful hardware designs
• Generates diverse, customizable Verilog code at scale
• Enables more effective fuzzing and testing of EDA tools
• Provides much-needed training data for language models in hardware design

For engineering teams, this work offers a practical solution to expand test suites, improve robustness of development tools, and potentially accelerate LLM applications in hardware design workflows.

Bottom-Up Generation of Verilog Designs for Testing EDA Tools